یک راهکار جدید برای کاهش جریان نشتی در کلید های CMOS

CMOS switches are one of the main components of today's analog circuits. Among the many types of non-idealities that can affect the performance of the switch, its leakage current is of utmost importance. In order to reduce the leakage current or equally increase the OFF resistance of any switch, a novel technique is presented in this paper. The proposed technique employs the body effect to increase the threshold voltage and it can be used at high-frequency or low-frequency switching circuits. In addition to the leakage current reduction, the presented technique also decreases the parasitic capacitance of the switch and the leakage current caused by the punch-through effect. The proposed switch is simulated by HSPICE using a commercial 0.18μm CMOS technology. Simulation results show more than 400% reduction in the leakage current compared to the NMOS switch and more than 300% reduction compared to the boot-strapped switch.